The present invention relates to a reduced instruction set computer type microprocessor.
Microprocessors are broadly classified into reduced instruction set computer (RISC) type and complex instruction set computer (CISC) type microprocessors. For an example of a RISC type microprocessor, reference may be made to "Am 29000" published in February 1987 by Advanced Micro Devices, Inc.
A RISC type microprocessor has a set of simple instructions for the sake of hardware simplification and can perform the processing of each stage of an instruction within one clock cycle by processing each instruction under pipeline control of hardware.
By contrast, a CISC type microprocessor, having a set of functionally complex instructions, which are executed under microprogram control, results in the fact that most of the instructions require a plurality of clock cycles to be executed. A set of functionally complex instructions can be divided into sets of simple instructions for use by a RISC type microprocessor. Therefore, a high-level language program is reformed by a compiler into groups of simple instructions, each optimized for an individual program. As a result, a RISC type microprocessor permits hardware simplification and performance improvement compared with a CISC type microprocessor.
To simplify the functions of instructions, a RISC type processor uses the following load/store formula. Where instructions to process memory data are concerned, this load/store formula consists only of a load instruction for reading the data of a memory out to an internal register and a store instruction for storing the data of the internal register into the memory.
In a microprocessor using such a RISC type load/store formula, arithmetic operation of data in the internal register with data from the memory, and storing the results the arithmetic operation into the internal register, require two steps, a load instruction and an instruction for arithmetic operation between registers.
In a pipeline-controlled microprocessor, if there is no executable instruction in any of the stages of logical address formation, conversion from a logical to a physical address and memory access results in a loss of CPU time. Instruction for arithmetic operation between data from an internal register and data from a memory is a frequently used instruction. Accordingly, there is a disadvantage that the efficiency of memory use in the performance aspect is prevented from improvement by the loss of CPU time and by the high frequency of instruction use.
In a CISC type microprocessor, no effective instruction can be interposed between a load instruction and an arithmetic instruction, and, accordingly, a longer time is required for the execution of instructions. To avoid this disadvantage, there is conceivable a structure to permit parallel operation of the address generating section and the arithmetic executing section. This structure, however, entails separate control of the address generating section and the arithmetic executing section, inviting greater complexity of both control and hardware composition.